Effect of RTL Coding Style On Testability*

A Testability Analysis Method for Register-Transfer Level Descriptions

| In this paper, we propose a new testability analysis method for Register-Transfer Level(RTL) descriptions. The proposed method is based on the idea of testability analysis in terms of dataow and control structure which can be extracted from RTL designs. We analyze testability of RTL descriptions with more testability measures than those of conventional gate-level testability, so that the meth...

Principles of verifiable RTL design - a functional coding style supporting verification processes in Verilog

Sensitivity to SEUs Evaluation using Probabilistic Testability Analysis at RTL

This work presents probabilistic methods for testability analysis at RTL and their use to evaluate the sensitivity of a digital circuit to Single Event Upsets (SEUs). A new probabilistic testability metric is proposed, in order to evaluate if the possible changes caused by SEUs are ignored or propagated by the dynamic behavior of the circuit. The new metric, event detectability, is defined base...

Testability Guided Hierarchical Test Generation with Decision Diagrams

A unified approach is presented for calculation multi-level testability measures and for testability guided hierarchical automated test pattern generation (ATPG) for digital systems. The methods and algorithms are based on path tracing procedures on decision diagrams. On the higher level the system is presented as a network of register transfer level (RTL) components, and on the lower level eac...

Testability Improvements Based on the Combination of Analytical and Evolutionary Approaches at RT Level

In the paper a new heuristic approach to the RTL testability analysis is presented. It is shown how the values of controllability/observability factors reflecting the structure of the circuit and other factors can be utilised to find solutions which are sub-optimal but still acceptable for the designer. The goal of the methodology is to enable the identification of such testability solutions wh...